? semiconductor components industries, llc, 2013 july, 2013 ? rev. 5 1 publication order number: NTD5407N/d NTD5407N, std5407n power mosfet 40 v, 38 a, single n ? channel, dpak features ? low r ds(on) ? high current capability ? low gate charge ? aec ? q101 qualified and ppap capable ? std5407n ? these devices are pb ? free and are rohs compliant applications ? electronic brake systems ? electronic power steering ? bridge circuits maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain ? to ? source voltage v dss 40 v gate ? to ? source voltage v gs 20 v continuous drain current ? r jc steady state t c = 25 c i d 38 a t c = 100 c 27 power dissipation ? r jc steady state t c = 25 c p d 75 w continuous drain current r ja (note 1) steady state t a = 25 c i d 7.6 a t a = 100 c 5.3 power dissipation ? r ja (note 1) steady state t a = 25 c p d 2.9 w pulsed drain current t p = 10 s i dm 75 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s 36 a single pulse drain ? to source avalanche energy ? (v dd = 50 v, v gs = 10 v, i pk = 17 a, l = 1 mh, r g = 25 ) eas 150 mj lead temperature for soldering purposes (1/8? from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. thermal resistance ratings (note 1) parameter symbol max unit junction ? to ? case (drain) r jc 2.0 c/w junction ? to ? ambient (note 1) r ja 52 c/w 1. surface mounted on fr4 board using 1 sq in pad size, (cu area 1.127 sq in [2 oz] including traces). http://onsemi.com marking diagram v (br)dss r ds(on) typ i d max (note 1) 40 v 21 m @ 10 v 38 a dpak case 369c style 2 n ? channel d s g 1 yww 54 07ng device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. y = year ww = work week 5407n = specific device code g = pb ? free device std5407nt4g dpak (pb ? free) 2500 / tape & reel 1 2 3 4 NTD5407Nt4g dpak (pb ? free) 2500 / tape & reel
NTD5407N, std5407n http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise stated) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 40 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 39 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 40 v t j = 25 c 1.0 a t j = 100 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 30 v 100 na on characteristics (note 2) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 3.5 v gate threshold temperature coefficient v gs(th) /t j ? 6.0 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 20 a 21 26 m v gs = 5.0 v, i d = 10 a 32 40 forward transconductance g fs v gs = 10 v, i d = 18 a 15 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 32 v 615 1000 pf output capacitance c oss 173 reverse transfer capacitance c rss 80 total gate charge q g(tot) v gs = 10 v, v ds = 32 v, i d = 38 a 20 nc gate ? to ? source charge q gs 2.25 gate ? to ? drain charge q gd 10.5 switching characteristics, v gs = 10 v (note 3) turn ? on delay time t d(on) v gs = 10 v, v dd = 32 v, i d = 38 a, r g = 2.5 6.8 ns rise time t r 17 turn ? off delay time t d(off) 66 fall time t f 51 switching characteristics, v gs = 5 v (note 3) turn ? on delay time t d(on) v gs = 5 v, v dd = 20 v, i d = 20 a, r g = 2.5 10 ns rise time t r 175 turn ? off delay time t d(off) 13 fall time t f 23 drain ? source diode characteristics (note 2) forward diode voltage v sd v gs = 0 v, i s = 5.0 a t j = 25 c 0.9 1.1 v t j = 125 c 0.75 reverse recovery time t rr v gs = 0 v, di s /dt = 100 a/ s, i s = 15 a 38 ns charge time t a 20.5 discharge time t b 17 reverse recovery charge q rr 40 nc 2. pulse test: pulse width 300 s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperatures.
NTD5407N, std5407n http://onsemi.com 3 typical performance curves t j = 100 c 02 v ds , drain ? to ? source voltage (volts) i d, drain current (amps) 0 figure 1. on ? region characteristics 3 20 0 figure 2. transfer characteristics v gs , gate ? to ? source voltage (volts) figure 3. on ? resistance vs. gate ? to ? source voltage r ds(on), drain ? to ? source resistance ( ) i d, drain current (amps) figure 4. on ? resistance vs. drain current and gate voltage i d, drain current (amps) ? 50 0 ? 25 25 2 1 0.8 0.6 50 175 figure 5. on ? resistance variation with temperature t j , junction temperature ( c) t j = 25 c t j = ? 55 c 75 t j = 25 c i d = 20 a v gs = 10 v r ds(on), drain ? to ? source resistance (normalized) t j = 25 c r ds(on), drain ? to ? source resistance ( ) v gs = 10 v 1 figure 6. drain ? to ? source leakage current vs. voltage v ds , drain ? to ? source voltage (volts) v gs = 0 v i dss , leakage (na) t j = 100 c 4 v v gs = 5 v v ds 10 v 20 35 3.5 v 4 40 v gs = 7 v to 10 v 40 125 100 5 12 v gs , gate ? to ? source voltage (volts) 0.02 0.03 0.04 0.08 36 0.01 4 0.045 0.005 0.025 0.015 0.035 10000 610 12 20 30 25 1.8 25 4 5.5 v 0.05 8 40 35 40 60 i d = 38 a t j = 25 c 100 30 5 8 4.5 v 7 59 0.055 0.065 0.075 10 1.6 1.4 1.2 150 13 7 59 20 8 67 0 50 0.105 10 15 60 30 10 50 5 v 6 v 10 30 1000 10 t j = 175 c 0.07 0.06 10 11 0.085 0.095 15
NTD5407N, std5407n http://onsemi.com 4 typical performance curves figure 7. capacitance variation figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge 1 0 v sd , source ? to ? drain voltage (volts) figure 9. resistive switching time variation vs. gate resistance i s , source current (amps) v gs = 0 v t j = 25 c 14 figure 10. diode forward voltage vs. current 0.6 13 12 r g , gate resistance (ohms) 1 10 100 10 1 t, time (ns) v ds = 32 v i d = 38 a v gs = 10 v t r t d(on) 1000 t f t d(off) 11 v gs , gate-to-source voltage (volts) 0 9 0 q g , total gate charge (nc) 15 10 15 i d = 36 a t j = 25 c v gs q gs q gd qt 6 3 20 0.3 v ds , drain-to-source voltage (volts) 21 0 35 14 7 v ds v ds = 0 v v gs = 0 v 20 10 10 1200 0 gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) t j = 25 c c oss c iss c rss 0 v gs v ds 30 c rss c iss 100 0.9 1.2 1800 600 5 15 25 15 55 12 28 10 2 3 4 5 6 7 8 9 0.1 1 10 100 1000 0.1 1 10 100 v ds , drain ? to ? source voltage (v) i d , drain current (a) figure 11. maximum rated forward biased safe operating area r ds(on) limit thermal limit package limit v gs = 10 v single pulse t c = 25 c 1 ms 100 s 10 ms dc 10 s
NTD5407N, std5407n http://onsemi.com 5 typical performance curves r(t), effective transient thermal resistance t, time (s) figure 12. thermal response 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2
NTD5407N, std5407n http://onsemi.com 6 package dimensions dpak (single gauge) case 369c issue d style 2: pin 1. gate 2. drain 3. source 4. drain b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NTD5407N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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